Low-power clocking circuits

ABSTRACT

In switching a CMOS circuit comprising first and second switchable logic elements the first logic element is enabled so as to allow it to reach a steady logic state and the second logic element is not enabled until the first logic element reaches a substantially steady logic state. The current drawn by the circuit at any time is thereby reduced.

FIELD OF INVENTION

The present invention relates to the field of switching low powerelectronic circuits and particularly CMOS logic circuits. Moreparticularly, the present invention relates to reducing or minimisingthe current drawn by a switchable electronic circuit at any point intime, such as CMOS circuitry.

BACKGROUND

The basic CMOS logic gate, as its known to those skilled in the art,consumes essentially no or a relatively small amount of power, exceptwhen it is actually in a switching state (a change in input causes theoutput to change). Circuits including CMOS logic gates often comprise alarge number of such gates, synchronised to a single clock signal.Synchronous systems are preferred from a design standpoint, and theirsynchronous behaviour is believed to be well understood by peopleskilled in the art. All logic gates of such a circuit switchsimultaneously, and the load presented to the power source appears as ashort, heavy burst, synchronised with the clock. Compensation for thisheavy power drain, as a result of current flowing simultaneously intothese gates, often necessitates the use of a large supply reservoircapacitor in the power source. This large capacitor is oftenundesirable.

OBJECTS OF INVENTION

An object of the present invention is to provide a method and/or devicewherein the current drawn by a circuit is distributed over apredetermined period of time.

A further object of the present invention is to provide a device and/ormethod which has a reduced dependence on a charge storage reservoir whenswitching a circuit comprising a relatively large number of CMOS gates.

SUMMARY OF INVENTION

The present invention provides a method of switching a circuitcomprising a plurality of non or minimal power consumption logicelements, said circuit comprising at least a first switchable logicelement and a second switchable logic element, the method comprising thesteps of:

enabling said first logic element so as to allow said first logicelement to reach a steady logic state, enabling said second logicelement so as to allow said second logic element to reach a steady logicstate, wherein:

enabling of said second element is not commenced until said firstelement reaches a substantially steady logic state.

The present invention also provides a device for switching a circuitcomprising a plurality of non or minimal power consumption logicelements, said circuit comprising at least a first switchable elementand a second switchable element, said device comprising:

a timing means coupled to said first element and being adapted to enablesaid first element so as to allow said first element to reach a steadylogic state, said timing means further being coupled to said secondelement and being adapted to enable said second element so as to allowsaid second element to reach a steady logic state, wherein said timingmeans enables the second element after the first element reaches asubstantially steady logic state.

The present invention also provides a method and device as describedabove, wherein the enabling of each element is co-ordinated withsuccessive cycles of an AC power source.

The present invention also provides a method and device as describedabove, wherein high switching currents are drawn directly form an ACpower source.

The present invention also provides a method and device as describedabove, wherein enabling of each circuit or part thereof is provided in astaggered relationship.

The present invention also provides a method and device as describedabove, wherein, within each element, gates or groups of gates arefurther selectively enabled in a staggered relationship.

The above methods or device(s) may be included in a clocking circuit.The timing means of the device may also incorporate delay elements toenhance device timing.

The present invention may be applicable to I.C. circuits, or other lowcurrent drawing circuit, including passive transponders.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view of a 2-phase clocking circuit according tothe invention;

FIG. 2 is a schematic view of a modification of the circuit shown inFIG. 1;

FIG. 3 is a schematic view of another modification of the circuit shownin FIG. 1; and

FIG. 4 is a schematic view of a complete circuit in which the inventionis adapted for use.

DISCLOSURE OF INVENTION

The present invention discloses tow arrangements and methods which maybe incorporated in a switchable circuit. The circuit may include groupsof circuit elements or sub-groups thereof (gates), each of which can beindividually switched when desired. The present invention deals withclocking a circuit in a particular way to reduce the energy storagerequirements of a power supply storage capacitor. One arrangement has ageneral application, while the other arrangement is usable where thecircuit is powered from a rectified AC source, having a frequency equalto an exact even multiple of a clock source.

Either or both arrangements may be used in any given application.

One arrangement may be termed "Staggered Clocks". This arrangementserves to cause successive sections of the circuit to switch atdifferent times, thereby "evening out" the load or current drawn on thepower supply. The staggered clocks arrangement will be described withreference to a 2-phase clocking scheme, however, it may be extended topolyphase clocks. This arrangement essentially trades speed for power.Therefore, it is of more use where low processing speed is desirable.

A 2-phase clocking scheme is shown in FIG. 1. The two clock phases, Ph-1and Ph-2 enable or switch alternate sections of the logic. All elementsor gates activated by Ph-1 are enabled, and allowed to reach their finalvalues, before Ph-1 terminates. At this point, the newly-determinedvalues are retained. Ph-2 then becomes active, and the new values areused in the second section of the logic, to evaluate further results,which may in turn serve as inputs to the Ph-1 logic on the nextoccurrence of Ph-1.

All clock phases must never be active simultaneously or else a "race"condition will result.

FIG. 1 shows that such a circuit will draw heavy load (Idd) from itssupply at the start of each of the clock phases, as the clock lineschange status, after which the circuits become steady state.

To more evenly distribute the current drawn from the power supply byenabled circuit elements, an arrangement in accordance with the presentinvention and exemplified by that shown in FIG. 2 may be employed. Herethe clocks have been divided into two sections each (more sections maybe used if desired). these sub-clocks are displaced in time, andaccordingly, spreading-out current drawn form the power supply, asshown. It is of an advantage if clock Ph-1.2 did not change status untilclock Ph-1.1 had stabilised. Coincident clocks will only serve to reducethe effect of the present invention.

To ensure correct circuit functioning, all the Ph-1 clocks must besimultaneously active long enough for the circuits to reach steady logicstates, and all Ph-1 clocks must be inactive before the first Ph-2 clockbecomes active. A similar rule holds for the Ph-2 clocks.

If the clocks are obtained by division from a high-frequency source, thestaggered clock may be obtained by conventional digital means (e.g.shift registers).

If such a high frequency source is not available, a chain of delayelements, such as ring-oscillator stages, may serve to stagger theclocks. In the case of VLSI, a further arrangement may be used bydistributing the clock in polysilicon, deliberately exploiting the highdistributed resistance and capacitance of that medium, in order tocreate desired staggered delays.

In each case, the latest (most delayed) of the sub-clocks may be used toinitiate the next switching-phase, to ensure there is not overlap.

Another arrangement relies on a Rectified AC Power Source. DC operatingpower can be obtained from a rectified AC power source of sufficientlylow internal impedance, and provided the AC frequency is equal to anexact even multiple of the clock frequency. (As before, we here considera 2-phase clocking scheme. In the general case, with N clock phases, theAC power frequency must equal (N x M x the clock frequency)/C, where Mand C are both integers, N as stated is the number of clock phases, C isthe number of rectifier conduction "events" per AC cycle (on for halfwave, two for full wave, etc.) and M is any number not less than one).

This arrangement utilises a concept wherein to phase-lock the clocks tothe AC waveform, each clock commences its active edge just as (orshortly after) the power rectifier begins to conduct. In essence, theheavy current pulse required to activate the logic, is drawn directlyform the AC supply, rather than from a DC reservoir capacitor.

FIGS. 3 and 4 show an example of a half-wave rectifier, and a 2-phaseclock using this arrangement, the timing means to co-ordinate circuitclocking being incorporated in the ASIC.

FIG. 3 shows the clock waveforms, together with the conduction angle ofthe supply rectifier. Comparison of this diagram with the schematic inFIG. 4 will show that the heavy current pulses of FIG. 1 are nowsupplied directly via the rectifier, while the reservoir capacitor isrequired merely to sustain the DC rail during the remainder of a clockperiod. Accordingly, the capacitor can be of a much smaller size.

This device may be especially useful in devices which are powered by ACmagnetic induction, using a resonant power pickup circuit, such as thoseused in passive transponder devices, and disclosed in copending PCTApplication Nos. PCT/AU88/00449 entitled "TRANSPONDER" andPCT/AU88/00476 entitled "POWERING AND COMMUNICATION APPARATUS ANDMETHOD". In such cases (assuming a moderate Q-factor in the tunedcircuit), the rectifier merely `taps into` the comparatively largecirculating currents in the tuned circuit at the appropriate times whenthe rectifier is conducting to obtain the current pulses required duringswitching of the circuit elements and gates.

I claim:
 1. A method of switching a circuit comprising a plurality ofnon or minimal power consumption logic elements, said circuit comprisingat least a first switchable CMOS logic element and a second switchableCMOS logic element, the method comprising the steps of:enabling saidfirst logic element to allow said first logic element to reach a steadylogic state, and enabling said second logic element when said firstlogic element reaches a substantially steady logic state, the enablingof each element being substantially coordinated with cycles of an ACpower source.
 2. A method as claimed in claim 1 wherein each enablingstep substantially corresponds to a peak of said AC cycles.
 3. A methodas claimed in claim 1 wherein said power source includes a tuned circuitand a storage capacitor coupled thereto.
 4. A method as claimed in claim1 wherein high switching currents are drawn directly form the AC powersource.
 5. A method as claimed in claim 1 wherein enabling of eachcircuit is provided by staggered clocks.
 6. A method as claimed in claim5 wherein, within each element, a selected number of gates isselectively enabled in a staggered relationship.
 7. A device forswitching a circuit comprising a plurality of non or minimal powerconsumption logic elements, said circuit comprising at least a firstswitchable CMOS logic element and a second switchable CMOS logicelement, said device comprising:timing means coupled to said firstelement for enabling said first element to reach a steady logic state,said timing means further being coupled to said second element forenabling said second element to reach a steady logic state when thefirst element reaches a substantially steady logic state, and means forcoupling each of said elements to an AC power source, the enabling ofeach element being substantially coordinated with cycles of an AC powersource.
 8. A device as claimed in claim 7 wherein said timing meanscomprises a polyphase clock for staggering circuit switching.
 9. Adevice as claimed in claim 7 wherein said timing means is phase-lockedto an Ac power waveform to enable each element at substantially a peakof said AC cycles.